A 1.1.6 Pipelining (HL Only)
A single core working through one instruction at a time leaves most of its hardware idle: while the arithmetic logic unit is busy, the circuitry that fetches and decodes instructions has nothing to do. Pipelining puts that idle hardware to work by overlapping the stages of several instructions, so a core can have a number of instructions in progress at once. A multi-core processor multiplies the effect, because every...